vgaflag Project Status
Project File: VGA.xise Parser Errors: No Errors
Module Name: vgaflag Implementation State: Programming File Generated
Target Device: xc3s250e-4cp132
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
27 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 27 4,896 1%  
Number of 4 input LUTs 40 4,896 1%  
Number of occupied Slices 33 2,448 1%  
    Number of Slices containing only related logic 33 33 100%  
    Number of Slices containing unrelated logic 0 33 0%  
Total Number of 4 input LUTs 59 4,896 1%  
    Number used as logic 40      
    Number used as a route-thru 19      
Number of bonded IOBs 11 92 11%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 2.99      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri May 15 22:40:08 202001 Warning (0 new)0
Translation ReportCurrentFri May 15 22:40:13 2020000
Map ReportCurrentFri May 15 22:40:17 2020018 Warnings (0 new)2 Infos (0 new)
Place and Route ReportCurrentFri May 15 22:40:24 2020002 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentFri May 15 22:40:27 2020006 Infos (0 new)
Bitgen ReportCurrentFri May 15 22:40:32 202008 Warnings (0 new)0
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentFri May 15 22:40:32 2020
WebTalk Log FileCurrentFri May 15 22:40:34 2020

Date Generated: 05/17/2020 - 14:02:14