keyboardtest Project Status (05/15/2020 - 21:50:57)
Project File: Tastatura.xise Parser Errors: No Errors
Module Name: keyboardtest Implementation State: Programming File Generated
Target Device: xc3s250e-4cp132
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
2 Warnings (1 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 77 4,896 1%  
Number of 4 input LUTs 48 4,896 1%  
Number of occupied Slices 77 2,448 3%  
    Number of Slices containing only related logic 77 77 100%  
    Number of Slices containing unrelated logic 0 77 0%  
Total Number of 4 input LUTs 112 4,896 2%  
    Number used as logic 48      
    Number used as a route-thru 64      
Number of bonded IOBs 15 92 16%  
Number of BUFGMUXs 3 24 12%  
Average Fanout of Non-Clock Nets 2.23      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri May 15 21:50:08 2020003 Infos (2 new)
Translation ReportCurrentFri May 15 21:50:34 2020000
Map ReportCurrentFri May 15 21:50:38 2020002 Infos (0 new)
Place and Route ReportCurrentFri May 15 21:50:47 202002 Warnings (1 new)2 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentFri May 15 21:50:50 2020006 Infos (0 new)
Bitgen ReportCurrentFri May 15 21:50:55 2020000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentFri May 15 21:50:55 2020
WebTalk Log FileCurrentFri May 15 21:50:57 2020

Date Generated: 05/15/2020 - 21:50:57