Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan3E
OS Platform: NT64 Target Device: xc3s250e
Project ID (random number) 900e7d6ff19f414199a199ecfa0ade8f.CEC596E75300497AB3C3651C0B6ACFAF.40 Target Package: cp132
Registration ID __0_0_0 Target Speed: -4
Date Generated 2019-05-22T21:23:18 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i5-4288U CPU @ 2.60GHz CPU Speed 2594 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Counters=1
  • 26-bit up counter=1
Registers=27
  • Flip-Flops=27
MiscellaneousStatistics
  • AGG_BONDED_IO=16
  • AGG_IO=16
  • AGG_SLICE=19
  • NUM_4_INPUT_LUT=30
  • NUM_BONDED_IBUF=5
  • NUM_BONDED_IOB=11
  • NUM_BUFGMUX=1
  • NUM_CYMUX=15
  • NUM_LUT_RT=15
  • NUM_SLICEL=19
  • NUM_SLICE_FF=29
  • NUM_XOR=16
NetStatistics
  • NumNets_Active=63
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=17
  • NumNodesOfType_Active_CNTRLPIN=7
  • NumNodesOfType_Active_DOUBLE=68
  • NumNodesOfType_Active_DUMMY=61
  • NumNodesOfType_Active_DUMMYESC=5
  • NumNodesOfType_Active_GLOBAL=7
  • NumNodesOfType_Active_HFULLHEX=1
  • NumNodesOfType_Active_HUNIHEX=10
  • NumNodesOfType_Active_INPUT=86
  • NumNodesOfType_Active_IOBOUTPUT=5
  • NumNodesOfType_Active_OMUX=40
  • NumNodesOfType_Active_OUTPUT=42
  • NumNodesOfType_Active_PREBXBY=11
  • NumNodesOfType_Active_VFULLHEX=4
  • NumNodesOfType_Active_VLONG=1
  • NumNodesOfType_Active_VUNIHEX=4
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_VCCOUT=1
SiteStatistics
  • IBUF-DIFFM=2
  • IBUF-DIFFMI=1
  • IBUF-IOB=2
  • IOB-DIFFM=5
  • IOB-DIFFS=6
  • SLICEL-SLICEM=6
SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IBUF=5
  • IBUF_INBUF=5
  • IBUF_PAD=5
  • IOB=11
  • IOB_OUTBUF=11
  • IOB_PAD=11
  • SLICEL=19
  • SLICEL_C1VDD=1
  • SLICEL_CYMUXF=8
  • SLICEL_CYMUXG=7
  • SLICEL_F=13
  • SLICEL_F5MUX=2
  • SLICEL_FFX=16
  • SLICEL_FFY=13
  • SLICEL_G=17
  • SLICEL_GNDF=7
  • SLICEL_GNDG=7
  • SLICEL_XORF=8
  • SLICEL_XORG=8
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:5]
IOB
  • O1=[O1_INV:4] [O1:7]
IOB_OUTBUF
  • IN=[IN_INV:4] [IN:7]
IOB_PAD
  • DRIVEATTRBOX=[12:11]
  • IOATTRBOX=[LVCMOS25:11]
  • SLEW=[SLOW:11]
SLICEL
  • BX=[BX_INV:1] [BX:5]
  • BY=[BY:2] [BY_INV:0]
  • CE=[CE:7] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:7]
  • CLK=[CLK:17] [CLK_INV:0]
SLICEL_CYMUXF
  • 0=[0:8] [0_INV:0]
  • 1=[1_INV:0] [1:8]
SLICEL_CYMUXG
  • 0=[0:7] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:2] [S0_INV:0]
SLICEL_FFX
  • CE=[CE:6] [CE_INV:0]
  • CK=[CK:16] [CK_INV:0]
  • D=[D:15] [D_INV:1]
  • FFX_INIT_ATTR=[INIT0:15] [INIT1:1]
  • FFX_SR_ATTR=[SRLOW:16]
  • LATCH_OR_FF=[FF:16]
  • SYNC_ATTR=[ASYNC:16]
SLICEL_FFY
  • CE=[CE:3] [CE_INV:0]
  • CK=[CK:13] [CK_INV:0]
  • D=[D:13] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:13]
  • FFY_SR_ATTR=[SRLOW:13]
  • LATCH_OR_FF=[FF:13]
  • SYNC_ATTR=[ASYNC:13]
SLICEL_XORF
  • 1=[1_INV:0] [1:8]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
IBUF
  • I=5
  • PAD=5
IBUF_INBUF
  • IN=5
  • OUT=5
IBUF_PAD
  • PAD=5
IOB
  • O1=11
  • PAD=11
IOB_OUTBUF
  • IN=11
  • OUT=11
IOB_PAD
  • PAD=11
SLICEL
  • BX=6
  • BY=2
  • CE=7
  • CIN=7
  • CLK=17
  • COUT=7
  • F1=13
  • F2=5
  • F3=4
  • F4=3
  • G1=17
  • G2=9
  • G3=6
  • G4=3
  • X=1
  • XQ=16
  • Y=4
  • YQ=13
SLICEL_C1VDD
  • 1=1
SLICEL_CYMUXF
  • 0=8
  • 1=8
  • OUT=8
  • S0=8
SLICEL_CYMUXG
  • 0=7
  • 1=7
  • OUT=7
  • S0=7
SLICEL_F
  • A1=13
  • A2=5
  • A3=4
  • A4=3
  • D=13
SLICEL_F5MUX
  • F=2
  • G=2
  • OUT=2
  • S0=2
SLICEL_FFX
  • CE=6
  • CK=16
  • D=16
  • Q=16
SLICEL_FFY
  • CE=3
  • CK=13
  • D=13
  • Q=13
SLICEL_G
  • A1=17
  • A2=9
  • A3=6
  • A4=3
  • D=17
SLICEL_GNDF
  • 0=7
SLICEL_GNDG
  • 0=7
SLICEL_XORF
  • 0=8
  • 1=8
  • O=8
SLICEL_XORG
  • 0=8
  • 1=8
  • O=8
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-4 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s250e-cp132-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 78 75 0 0 0 0 0
bitgen 256 256 0 0 0 0 0
map 258 254 0 0 0 0 0
ngcbuild 9 9 0 0 0 0 0
ngdbuild 264 264 0 0 0 0 0
obngc 9 9 0 0 0 0 0
par 254 254 0 0 0 0 0
trce 254 254 0 0 0 0 0
xst 390 390 0 0 0 0 0
 
Help Statistics
Search words with results
buf ( 1 ) logic gates ( 1 )
nand ( 1 )
Help files
/doc/usenglish/isehelp/ise_c_using_design_constraints.htm ( 4 ) /doc/usenglish/isehelp/ite_c_overview.htm ( 3 )
/doc/usenglish/isehelp/rtv_c_overview.htm ( 1 ) /doc/usenglish/isehelp/sse_p_adding_buffer.htm ( 1 )
http://www.xilinx.com/cgi-bin/docs/rdoc?l=en;v=14.7;d=xst.pdf ( 1 )
 
Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000 PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values PROP_SelectedInstanceHierarchicalPath=/displej7segment
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2019-04-14T23:55:01
PROP_intWbtProjectID=CEC596E75300497AB3C3651C0B6ACFAF PROP_intWbtProjectIteration=40
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_selectedSimRootSourceNode_behav=work.displej7segment
PROP_xilxBitgStart_Clk=JTAG Clock PROP_xilxBitgStart_IntDone=true
PROP_AutoTop=true PROP_DevFamily=Spartan3E
PROP_DevDevice=xc3s250e PROP_DevFamilyPMName=spartan3e
PROP_DevPackage=cp132 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-4 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=20 NGDBUILD_NUM_FDE=9 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=4 NGDBUILD_NUM_INV=6 NGDBUILD_NUM_LUT1=15 NGDBUILD_NUM_LUT2=4
NGDBUILD_NUM_LUT3=2 NGDBUILD_NUM_LUT3_D=1 NGDBUILD_NUM_LUT3_L=1 NGDBUILD_NUM_LUT4=6
NGDBUILD_NUM_MUXCY=15 NGDBUILD_NUM_MUXF5=2 NGDBUILD_NUM_OBUF=11 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=16
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=20 NGDBUILD_NUM_FDE=9 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=4 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=6 NGDBUILD_NUM_LUT1=15
NGDBUILD_NUM_LUT2=4 NGDBUILD_NUM_LUT3=2 NGDBUILD_NUM_LUT3_D=1 NGDBUILD_NUM_LUT3_L=1
NGDBUILD_NUM_LUT4=6 NGDBUILD_NUM_MUXCY=15 NGDBUILD_NUM_MUXF5=2 NGDBUILD_NUM_OBUF=11
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=16
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s250e-4-cp132 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=100000 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5