displej7segment Project Status
Project File: Zadatak4Verilog.xise Parser Errors: No Errors
Module Name: displej7segment Implementation State: Programming File Generated
Target Device: xc3s250e-4cp132
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
23 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 32 4,896 1%  
Number of 4 input LUTs 27 4,896 1%  
Number of occupied Slices 23 2,448 1%  
    Number of Slices containing only related logic 23 23 100%  
    Number of Slices containing unrelated logic 0 23 0%  
Total Number of 4 input LUTs 42 4,896 1%  
    Number used as logic 27      
    Number used as a route-thru 15      
Number of bonded IOBs 20 92 21%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 2.45      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu May 30 10:53:57 2019022 Warnings (0 new)1 Info (0 new)
Translation ReportCurrentThu May 30 10:55:51 2019000
Map ReportCurrentThu May 30 10:55:56 2019002 Infos (0 new)
Place and Route ReportCurrentThu May 30 10:56:03 201901 Warning (0 new)2 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentThu May 30 10:56:07 2019006 Infos (0 new)
Bitgen ReportCurrentThu May 30 10:56:11 2019000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentThu May 30 10:56:11 2019
WebTalk Log FileCurrentThu May 30 10:56:16 2019

Date Generated: 06/02/2019 - 10:19:59