displej7segment Project Status | |||
Project File: | Zadatak4Verilog.xise | Parser Errors: | No Errors |
Module Name: | displej7segment | Implementation State: | Programming File Generated |
Target Device: | xc3s250e-4cp132 |
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Product Version: | ISE 14.7 |
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Design Goal: | Balanced |
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All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
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All Constraints Met |
Environment: | System Settings |
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0 (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 39 | 4,896 | 1% | ||
Number of 4 input LUTs | 12 | 4,896 | 1% | ||
Number of occupied Slices | 23 | 2,448 | 1% | ||
Number of Slices containing only related logic | 23 | 23 | 100% | ||
Number of Slices containing unrelated logic | 0 | 23 | 0% | ||
Total Number of 4 input LUTs | 37 | 4,896 | 1% | ||
Number used as logic | 12 | ||||
Number used as a route-thru | 25 | ||||
Number of bonded IOBs | 12 | 92 | 13% | ||
Number of BUFGMUXs | 1 | 24 | 4% | ||
Average Fanout of Non-Clock Nets | 1.86 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Wed May 22 19:43:08 2019 | 0 | 0 | 2 Infos (2 new) | |
Translation Report | Current | Wed May 22 19:43:14 2019 | 0 | 0 | 0 | |
Map Report | Current | Wed May 22 19:43:18 2019 | ||||
Place and Route Report | Current | Wed May 22 19:43:25 2019 | 0 | 1 Warning (1 new) | 2 Infos (2 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | Wed May 22 19:43:28 2019 | 0 | 0 | 6 Infos (6 new) | |
Bitgen Report | Current | Wed May 22 19:43:32 2019 | 0 | 0 | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Current | Wed May 22 19:43:33 2019 | |
WebTalk Log File | Current | Wed May 22 19:43:37 2019 |