displej7segment Project Status
Project File: Zadatak4Verilog.xise Parser Errors: No Errors
Module Name: displej7segment Implementation State: Programming File Generated
Target Device: xc3s250e-4cp132
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
1 Warning (1 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 30 4,896 1%  
Number of 4 input LUTs 11 4,896 1%  
Number of occupied Slices 19 2,448 1%  
    Number of Slices containing only related logic 19 19 100%  
    Number of Slices containing unrelated logic 0 19 0%  
Total Number of 4 input LUTs 36 4,896 1%  
    Number used as logic 11      
    Number used as a route-thru 25      
Number of bonded IOBs 16 92 17%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 1.65      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed May 22 17:39:39 2019001 Info (1 new)
Translation ReportCurrentWed May 22 17:39:44 2019000
Map ReportCurrentWed May 22 17:39:49 2019002 Infos (2 new)
Place and Route ReportCurrentWed May 22 17:39:57 201901 Warning (1 new)2 Infos (2 new)
Power Report     
Post-PAR Static Timing ReportCurrentWed May 22 17:40:00 2019006 Infos (6 new)
Bitgen ReportCurrentWed May 22 17:40:04 2019000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentWed May 22 17:40:05 2019
WebTalk Log FileCurrentWed May 22 17:40:06 2019

Date Generated: 05/23/2019 - 09:28:16