displej7segment Project Status | |||
Project File: | Zadatak4Verilog.xise | Parser Errors: | No Errors |
Module Name: | displej7segment | Implementation State: | Programming File Generated |
Target Device: | xc3s250e-4cp132 |
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No Errors |
Product Version: | ISE 14.7 |
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No Warnings |
Design Goal: | Balanced |
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All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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0 (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of 4 input LUTs | 7 | 4,896 | 1% | ||
Number of occupied Slices | 4 | 2,448 | 1% | ||
Number of Slices containing only related logic | 4 | 4 | 100% | ||
Number of Slices containing unrelated logic | 0 | 4 | 0% | ||
Total Number of 4 input LUTs | 7 | 4,896 | 1% | ||
Number of bonded IOBs | 19 | 92 | 20% | ||
Average Fanout of Non-Clock Nets | 2.60 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Thu May 9 12:06:47 2019 | 0 | 0 | 0 | |
Translation Report | Current | Thu May 9 12:06:52 2019 | 0 | 0 | 0 | |
Map Report | Current | Thu May 9 12:06:56 2019 | 0 | 0 | 2 Infos (2 new) | |
Place and Route Report | Current | Thu May 9 12:07:02 2019 | 0 | 0 | 1 Info (1 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | Thu May 9 12:07:05 2019 | 0 | 0 | 6 Infos (6 new) | |
Bitgen Report | Current | Thu May 9 12:07:09 2019 | 0 | 0 | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Current | Thu May 9 12:07:10 2019 | |
WebTalk Log File | Current | Thu May 9 12:07:14 2019 |