displej7segment Project Status
Project File: Zadatak4Verilog.xise Parser Errors: No Errors
Module Name: displej7segment Implementation State: Programming File Generated
Target Device: xc3s250e-4cp132
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of 4 input LUTs 7 4,896 1%  
Number of occupied Slices 4 2,448 1%  
    Number of Slices containing only related logic 4 4 100%  
    Number of Slices containing unrelated logic 0 4 0%  
Total Number of 4 input LUTs 7 4,896 1%  
Number of bonded IOBs 19 92 20%  
Average Fanout of Non-Clock Nets 2.60      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu May 9 12:06:47 2019000
Translation ReportCurrentThu May 9 12:06:52 2019000
Map ReportCurrentThu May 9 12:06:56 2019002 Infos (2 new)
Place and Route ReportCurrentThu May 9 12:07:02 2019001 Info (1 new)
Power Report     
Post-PAR Static Timing ReportCurrentThu May 9 12:07:05 2019006 Infos (6 new)
Bitgen ReportCurrentThu May 9 12:07:09 2019000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentThu May 9 12:07:10 2019
WebTalk Log FileCurrentThu May 9 12:07:14 2019

Date Generated: 05/22/2019 - 17:22:45