displej7segment Project Status
Project File: Zadatak4Verilog.xise Parser Errors: No Errors
Module Name: displej7segment Implementation State: Programming File Generated
Target Device: xc3s250e-4cp132
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 39 4,896 1%  
Number of 4 input LUTs 12 4,896 1%  
Number of occupied Slices 23 2,448 1%  
    Number of Slices containing only related logic 23 23 100%  
    Number of Slices containing unrelated logic 0 23 0%  
Total Number of 4 input LUTs 37 4,896 1%  
    Number used as logic 12      
    Number used as a route-thru 25      
Number of bonded IOBs 12 92 13%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 1.86      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed May 22 19:43:08 2019002 Infos (2 new)
Translation ReportCurrentWed May 22 19:43:14 2019000
Map ReportCurrentWed May 22 19:43:18 2019   
Place and Route ReportCurrentWed May 22 19:43:25 201901 Warning (1 new)2 Infos (2 new)
Power Report     
Post-PAR Static Timing ReportCurrentWed May 22 19:43:28 2019006 Infos (6 new)
Bitgen ReportCurrentWed May 22 19:43:32 2019000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentWed May 22 19:43:33 2019
WebTalk Log FileCurrentWed May 22 19:43:37 2019

Date Generated: 05/23/2019 - 10:02:41