test Project Status
Project File: Zadatak1Verilog.xise Parser Errors: No Errors
Module Name: test Implementation State: Programming File Generated
Target Device: xc3s250e-4cp132
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of 4 input LUTs 1 4,896 1%  
Number of occupied Slices 1 2,448 1%  
    Number of Slices containing only related logic 1 1 100%  
    Number of Slices containing unrelated logic 0 1 0%  
Total Number of 4 input LUTs 1 4,896 1%  
Number of bonded IOBs 3 92 3%  
Average Fanout of Non-Clock Nets 1.00      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Apr 17 23:12:33 2019000
Translation ReportCurrentWed Apr 17 23:12:38 2019000
Map ReportCurrentWed Apr 17 23:12:42 2019002 Infos (0 new)
Place and Route ReportCurrentWed Apr 17 23:12:47 2019001 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentWed Apr 17 23:12:50 2019006 Infos (0 new)
Bitgen ReportCurrentWed Apr 17 23:12:55 2019000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentWed Apr 17 23:12:55 2019
WebTalk Log FileCurrentWed Apr 17 23:12:59 2019

Date Generated: 05/08/2019 - 23:26:08