test Project Status (04/14/2019 - 21:25:21)
Project File: Zadatak1Verilog.xise Parser Errors: No Errors
Module Name: test Implementation State: Programming File Generated
Target Device: xc3s250e-4cp132
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
    Number of Slices containing only related logic 0 0 0%  
    Number of Slices containing unrelated logic 0 0 0%  
Number of bonded IOBs 2 92 2%  
Average Fanout of Non-Clock Nets 1.00      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Apr 21 09:20:13 2020000
Translation ReportCurrentTue Apr 21 09:20:22 2020000
Map ReportCurrentTue Apr 21 09:20:35 2020002 Infos (0 new)
Place and Route ReportCurrentTue Apr 21 09:20:47 2020001 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentTue Apr 21 09:20:52 2020006 Infos (0 new)
Bitgen ReportCurrentTue Apr 21 09:20:58 2020000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentTue Apr 21 09:20:59 2020
WebTalk Log FileCurrentTue Apr 21 09:21:02 2020

Date Generated: 06/01/2020 - 17:30:43