Project Statistics |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=Schematic |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2019-04-18T09:36:23 |
PROP_intWbtProjectID=C192FC8487264B6B8AD5D4CB4F8964A0 |
PROP_intWbtProjectIteration=1 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_lockPinsUcfFile=changed |
PROP_xilxBitgStart_Clk=JTAG Clock |
PROP_AutoTop=true |
PROP_DevFamily=Spartan3E |
PROP_DevDevice=xc3s250e |
PROP_DevFamilyPMName=spartan3e |
PROP_DevPackage=cp132 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-4 |
PROP_PreferredLanguage=Verilog |
FILE_SCHEMATIC=1 |
FILE_UCF=1 |