test Project Status | |||
Project File: | Zadatak1Sch.xise | Parser Errors: | No Errors |
Module Name: | test | Implementation State: | Programming File Generated |
Target Device: | xc3s250e-4cp132 |
|
No Errors |
Product Version: | ISE 14.7 |
|
6 Warnings (6 new) |
Design Goal: | Balanced |
|
All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
|
|
Environment: | System Settings |
|
0 (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slices containing only related logic | 0 | 0 | 0% | ||
Number of Slices containing unrelated logic | 0 | 0 | 0% | ||
Number of bonded IOBs | 2 | 92 | 2% | ||
Average Fanout of Non-Clock Nets | 1.00 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Sun Apr 14 22:52:33 2019 | 0 | 6 Warnings (6 new) | 0 | |
Translation Report | Current | Sun Apr 14 22:52:38 2019 | 0 | 0 | 0 | |
Map Report | Current | Sun Apr 14 22:52:44 2019 | 0 | 0 | 2 Infos (2 new) | |
Place and Route Report | Current | Sun Apr 14 22:52:50 2019 | 0 | 0 | 1 Info (1 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | Sun Apr 14 22:52:54 2019 | 0 | 0 | 6 Infos (6 new) | |
Bitgen Report | Current | Sun Apr 14 22:52:58 2019 | 0 | 0 | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Current | Sun Apr 14 22:52:59 2019 | |
WebTalk Log File | Current | Sun Apr 14 22:53:04 2019 |