test Project Status
Project File: Zadatak1VerilogO.xise Parser Errors: No Errors
Module Name: test Implementation State: Programming File Generated
Target Device: xc3s250e-4cp132
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of 4 input LUTs 1 4,896 1%  
Number of occupied Slices 1 2,448 1%  
    Number of Slices containing only related logic 1 1 100%  
    Number of Slices containing unrelated logic 0 1 0%  
Total Number of 4 input LUTs 1 4,896 1%  
Number of bonded IOBs 3 92 3%  
Average Fanout of Non-Clock Nets 1.00      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri Apr 19 00:21:18 2019000
Translation ReportCurrentFri Apr 19 00:21:27 2019000
Map ReportCurrentFri Apr 19 00:21:41 2019   
Place and Route ReportCurrentFri Apr 19 00:21:51 2019001 Info (1 new)
Power Report     
Post-PAR Static Timing ReportCurrentFri Apr 19 00:21:55 2019006 Infos (6 new)
Bitgen ReportCurrentFri Apr 19 00:22:01 2019000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentFri Apr 19 00:22:02 2019
WebTalk Log FileCurrentFri Apr 19 00:22:07 2019

Date Generated: 05/11/2020 - 08:09:15