LCD1 Project Status
Project File: LCD1.xise Parser Errors: No Errors
Module Name: LCD1 Implementation State: Programming File Generated
Target Device: xc3s250e-4cp132
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of 4 input LUTs 7 4,896 1%  
Number of occupied Slices 4 2,448 1%  
    Number of Slices containing only related logic 4 4 100%  
    Number of Slices containing unrelated logic 0 4 0%  
Total Number of 4 input LUTs 7 4,896 1%  
Number of bonded IOBs 19 92 20%  
Average Fanout of Non-Clock Nets 2.60      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Dec 22 14:39:31 2021000
Translation ReportCurrentWed Dec 22 14:39:36 2021000
Map ReportCurrentWed Dec 22 14:39:40 2021002 Infos (2 new)
Place and Route ReportCurrentWed Dec 22 14:39:46 2021001 Info (1 new)
Power Report     
Post-PAR Static Timing ReportCurrentWed Dec 22 14:39:49 2021006 Infos (6 new)
Bitgen ReportCurrentWed Dec 22 14:39:53 2021000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentWed Dec 22 14:39:54 2021
WebTalk Log FileCurrentWed Dec 22 14:39:58 2021

Date Generated: 12/27/2021 - 10:22:22