LCD4 Project Status
Project File: LCD4.xise Parser Errors: No Errors
Module Name: LCD4 Implementation State: Programming File Generated
Target Device: xc3s250e-4cp132
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
2 Warnings (2 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 43 4,896 1%  
Number of 4 input LUTs 17 4,896 1%  
Number of occupied Slices 27 2,448 1%  
    Number of Slices containing only related logic 27 27 100%  
    Number of Slices containing unrelated logic 0 27 0%  
Total Number of 4 input LUTs 49 4,896 1%  
    Number used as logic 17      
    Number used as a route-thru 32      
Number of bonded IOBs 12 92 13%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 2.28      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Dec 27 13:09:44 2021001 Info (0 new)
Translation ReportCurrentMon Dec 27 13:09:48 2021000
Map ReportCurrentMon Dec 27 13:09:52 2021002 Infos (0 new)
Place and Route ReportCurrentMon Dec 27 13:10:00 202102 Warnings (2 new)2 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentMon Dec 27 13:10:03 2021006 Infos (0 new)
Bitgen ReportCurrentMon Dec 27 13:10:07 2021000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentMon Dec 27 13:10:08 2021
WebTalk Log FileCurrentMon Dec 27 13:10:12 2021

Date Generated: 12/28/2021 - 11:24:52