Takt Project Status
Project File: Takt.xise Parser Errors: No Errors
Module Name: Takt Implementation State: Programming File Generated
Target Device: xc3s250e-4cp132
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 26 4,896 1%  
Number of 4 input LUTs 1 4,896 1%  
Number of occupied Slices 13 2,448 1%  
    Number of Slices containing only related logic 13 13 100%  
    Number of Slices containing unrelated logic 0 13 0%  
Total Number of 4 input LUTs 26 4,896 1%  
    Number used as logic 1      
    Number used as a route-thru 25      
Number of bonded IOBs 9 92 9%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 1.21      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Dec 22 13:57:50 2021000
Translation ReportCurrentWed Dec 22 13:57:55 2021000
Map ReportCurrentWed Dec 22 13:58:00 2021002 Infos (2 new)
Place and Route ReportCurrentWed Dec 22 13:58:08 2021002 Infos (2 new)
Power Report     
Post-PAR Static Timing ReportCurrentWed Dec 22 13:58:11 2021006 Infos (6 new)
Bitgen ReportCurrentWed Dec 22 13:58:16 2021000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentWed Dec 22 13:58:16 2021
WebTalk Log FileCurrentWed Dec 22 13:58:21 2021

Date Generated: 12/27/2021 - 10:08:50