Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan3E
OS Platform: NT64 Target Device: xc3s250e
Project ID (random number) 55f081c80867439fa39bd3bfaa43cdb7.CBA95F0E84584717ADDC5D8047A1C238.1 Target Package: cp132
Registration ID __0_0_0 Target Speed: -4
Date Generated 2021-12-22T14:39:53 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i5-4288U CPU @ 2.60GHz CPU Speed 2594 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
ROMs=1
  • 16x7-bit ROM=1
MiscellaneousStatistics
  • AGG_BONDED_IO=19
  • AGG_IO=19
  • AGG_SLICE=4
  • NUM_4_INPUT_LUT=7
  • NUM_BONDED_IBUF=8
  • NUM_BONDED_IOB=11
  • NUM_SLICEL=4
NetStatistics
  • NumNets_Active=34
  • NumNodesOfType_Active_DOUBLE=57
  • NumNodesOfType_Active_DUMMY=28
  • NumNodesOfType_Active_DUMMYESC=8
  • NumNodesOfType_Active_HFULLHEX=3
  • NumNodesOfType_Active_HUNIHEX=14
  • NumNodesOfType_Active_INPUT=39
  • NumNodesOfType_Active_IOBOUTPUT=8
  • NumNodesOfType_Active_OMUX=2
  • NumNodesOfType_Active_OUTPUT=7
  • NumNodesOfType_Active_PREBXBY=9
  • NumNodesOfType_Active_VFULLHEX=2
  • NumNodesOfType_Active_VLONG=2
  • NumNodesOfType_Active_VUNIHEX=8
SiteStatistics
  • IBUF-DIFFM=5
  • IBUF-IOB=2
  • IOB-DIFFM=5
  • IOB-DIFFS=6
  • SLICEL-SLICEM=2
SiteSummary
  • IBUF=8
  • IBUF_INBUF=8
  • IBUF_PAD=8
  • IOB=11
  • IOB_OUTBUF=11
  • IOB_PAD=11
  • SLICEL=4
  • SLICEL_F=3
  • SLICEL_G=4
 
Configuration Data
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:8]
IOB
  • O1=[O1_INV:4] [O1:7]
IOB_OUTBUF
  • IN=[IN_INV:4] [IN:7]
IOB_PAD
  • DRIVEATTRBOX=[12:11]
  • IOATTRBOX=[LVCMOS25:11]
  • SLEW=[SLOW:11]
 
Pin Data
IBUF
  • I=8
  • PAD=8
IBUF_INBUF
  • IN=8
  • OUT=8
IBUF_PAD
  • PAD=8
IOB
  • O1=11
  • PAD=11
IOB_OUTBUF
  • IN=11
  • OUT=11
IOB_PAD
  • PAD=11
SLICEL
  • F1=3
  • F2=3
  • F3=3
  • F4=3
  • G1=4
  • G2=4
  • G3=4
  • G4=4
  • X=3
  • Y=4
SLICEL_F
  • A1=3
  • A2=3
  • A3=3
  • A4=3
  • D=3
SLICEL_G
  • A1=4
  • A2=4
  • A3=4
  • A4=4
  • D=4
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s250e-cp132-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 26 26 0 0 0 0 0
arwz 1 1 0 0 0 0 0
bitgen 33 33 0 0 0 0 0
map 36 33 0 0 0 0 0
ngc2edif 1 1 0 0 0 0 0
ngdbuild 38 38 0 0 0 0 0
par 33 33 0 0 0 0 0
trce 33 33 0 0 0 0 0
xps 1 1 0 0 0 0 0
xst 62 62 0 0 0 0 0
 
Help Statistics
Search words with results
lut6 ( 1 )
Unsuccessful Search words
$readmemh ( 1 ) readmemh ( 1 )
Help files
/doc/usenglish/isehelp/ise_c_overview.htm ( 1 ) /doc/usenglish/isehelp/ite_c_overview.htm ( 1 )
/doc/usenglish/isehelp/rtv_db_lut_content.htm ( 1 ) /doc/usenglish/isehelp/rtv_p_rtl_lut_content.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2021-12-22T14:07:56
PROP_intWbtProjectID=CBA95F0E84584717ADDC5D8047A1C238 PROP_intWbtProjectIteration=1
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_xilxBitgStart_Clk=JTAG Clock
PROP_AutoTop=true PROP_DevFamily=Spartan3E
PROP_DevDevice=xc3s250e PROP_DevFamilyPMName=spartan3e
PROP_DevPackage=cp132 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-4 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_IBUF=8 NGDBUILD_NUM_INV=4 NGDBUILD_NUM_LUT4=7 NGDBUILD_NUM_OBUF=11
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_IBUF=8 NGDBUILD_NUM_INV=4 NGDBUILD_NUM_LUT4=7 NGDBUILD_NUM_OBUF=11
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s250e-4-cp132 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=500 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5