Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan3E
OS Platform: NT64 Target Device: xc3s250e
Project ID (random number) 55f081c80867439fa39bd3bfaa43cdb7.107415CD2C3647CF9D2ADFB4B666B5C8.1 Target Package: cp132
Registration ID __0_0_0 Target Speed: -4
Date Generated 2021-12-27T11:01:21 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i5-4288U CPU @ 2.60GHz CPU Speed 2594 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Counters=2
  • 26-bit up counter=1
  • 4-bit up counter=1
ROMs=1
  • 16x7-bit ROM=1
Registers=9
  • Flip-Flops=9
MiscellaneousStatistics
  • AGG_BONDED_IO=12
  • AGG_IO=12
  • AGG_SLICE=23
  • NUM_4_INPUT_LUT=37
  • NUM_BONDED_IBUF=1
  • NUM_BONDED_IOB=11
  • NUM_BUFGMUX=1
  • NUM_CYMUX=25
  • NUM_LUT_RT=25
  • NUM_SLICEL=23
  • NUM_SLICE_FF=39
  • NUM_XOR=26
NetStatistics
  • NumNets_Active=66
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=22
  • NumNodesOfType_Active_CNTRLPIN=7
  • NumNodesOfType_Active_DOUBLE=36
  • NumNodesOfType_Active_DUMMY=66
  • NumNodesOfType_Active_DUMMYESC=1
  • NumNodesOfType_Active_GLOBAL=6
  • NumNodesOfType_Active_HFULLHEX=2
  • NumNodesOfType_Active_INPUT=87
  • NumNodesOfType_Active_IOBOUTPUT=1
  • NumNodesOfType_Active_OMUX=51
  • NumNodesOfType_Active_OUTPUT=53
  • NumNodesOfType_Active_PREBXBY=6
  • NumNodesOfType_Active_VFULLHEX=4
  • NumNodesOfType_Active_VLONG=2
  • NumNodesOfType_Active_VUNIHEX=4
  • NumNodesOfType_Gnd_DOUBLE=1
  • NumNodesOfType_Gnd_INPUT=1
  • NumNodesOfType_Gnd_OUTPUT=1
  • NumNodesOfType_Gnd_PREBXBY=1
SiteStatistics
  • IBUF-DIFFMI=1
  • IOB-DIFFM=5
  • IOB-DIFFS=6
  • SLICEL-SLICEM=6
SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IBUF=1
  • IBUF_INBUF=1
  • IBUF_PAD=1
  • IOB=11
  • IOB_OUTBUF=11
  • IOB_PAD=11
  • SLICEL=23
  • SLICEL_C1VDD=1
  • SLICEL_CYMUXF=13
  • SLICEL_CYMUXG=12
  • SLICEL_F=17
  • SLICEL_FFX=17
  • SLICEL_FFY=22
  • SLICEL_G=20
  • SLICEL_GNDF=12
  • SLICEL_GNDG=12
  • SLICEL_XORF=13
  • SLICEL_XORG=13
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:1]
IOB
  • O1=[O1_INV:0] [O1:11]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:11]
IOB_PAD
  • DRIVEATTRBOX=[12:11]
  • IOATTRBOX=[LVCMOS25:11]
  • SLEW=[SLOW:11]
SLICEL
  • BX=[BX_INV:0] [BX:1]
  • BY=[BY:3] [BY_INV:0]
  • CE=[CE:4] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:12]
  • CLK=[CLK:22] [CLK_INV:0]
  • SR=[SR:3] [SR_INV:0]
SLICEL_CYMUXF
  • 0=[0:13] [0_INV:0]
  • 1=[1_INV:0] [1:13]
SLICEL_CYMUXG
  • 0=[0:12] [0_INV:0]
SLICEL_FFX
  • CE=[CE:3] [CE_INV:0]
  • CK=[CK:17] [CK_INV:0]
  • D=[D:17] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:17]
  • FFX_SR_ATTR=[SRLOW:17]
  • LATCH_OR_FF=[FF:17]
  • SYNC_ATTR=[ASYNC:17]
SLICEL_FFY
  • CE=[CE:4] [CE_INV:0]
  • CK=[CK:22] [CK_INV:0]
  • D=[D:22] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:21] [INIT1:1]
  • FFY_SR_ATTR=[SRLOW:22]
  • LATCH_OR_FF=[FF:22]
  • SR=[SR:3] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:19] [SYNC:3]
SLICEL_XORF
  • 1=[1_INV:0] [1:13]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
IBUF
  • I=1
  • PAD=1
IBUF_INBUF
  • IN=1
  • OUT=1
IBUF_PAD
  • PAD=1
IOB
  • O1=11
  • PAD=11
IOB_OUTBUF
  • IN=11
  • OUT=11
IOB_PAD
  • PAD=11
SLICEL
  • BX=1
  • BY=3
  • CE=4
  • CIN=12
  • CLK=22
  • COUT=12
  • F1=17
  • F2=4
  • F3=4
  • F4=4
  • G1=20
  • G2=7
  • G3=5
  • G4=4
  • SR=3
  • XQ=17
  • Y=1
  • YQ=22
SLICEL_C1VDD
  • 1=1
SLICEL_CYMUXF
  • 0=13
  • 1=13
  • OUT=13
  • S0=13
SLICEL_CYMUXG
  • 0=12
  • 1=12
  • OUT=12
  • S0=12
SLICEL_F
  • A1=17
  • A2=4
  • A3=4
  • A4=4
  • D=17
SLICEL_FFX
  • CE=3
  • CK=17
  • D=17
  • Q=17
SLICEL_FFY
  • CE=4
  • CK=22
  • D=22
  • Q=22
  • SR=3
SLICEL_G
  • A1=20
  • A2=7
  • A3=5
  • A4=4
  • D=20
SLICEL_GNDF
  • 0=12
SLICEL_GNDG
  • 0=12
SLICEL_XORF
  • 0=13
  • 1=13
  • O=13
SLICEL_XORG
  • 0=13
  • 1=13
  • O=13
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s250e-cp132-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 26 26 0 0 0 0 0
arwz 1 1 0 0 0 0 0
bitgen 36 36 0 0 0 0 0
map 39 36 0 0 0 0 0
ngc2edif 1 1 0 0 0 0 0
ngdbuild 41 41 0 0 0 0 0
par 36 36 0 0 0 0 0
trce 36 36 0 0 0 0 0
xps 1 1 0 0 0 0 0
xst 65 65 0 0 0 0 0
 
Help Statistics
Search words with results
lut6 ( 1 )
Unsuccessful Search words
$readmemh ( 1 ) readmemh ( 1 )
Help files
/doc/usenglish/isehelp/ise_c_overview.htm ( 1 ) /doc/usenglish/isehelp/ite_c_overview.htm ( 1 )
/doc/usenglish/isehelp/rtv_db_lut_content.htm ( 1 ) /doc/usenglish/isehelp/rtv_p_rtl_lut_content.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2021-12-27T10:39:11
PROP_intWbtProjectID=107415CD2C3647CF9D2ADFB4B666B5C8 PROP_intWbtProjectIteration=1
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_xilxBitgStart_Clk=JTAG Clock
PROP_AutoTop=true PROP_DevFamily=Spartan3E
PROP_DevDevice=xc3s250e PROP_DevFamilyPMName=spartan3e
PROP_DevPackage=cp132 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-4 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=29 NGDBUILD_NUM_FDE=7 NGDBUILD_NUM_FDR=3
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_INV=1 NGDBUILD_NUM_LUT1=25 NGDBUILD_NUM_LUT2=2
NGDBUILD_NUM_LUT3=1 NGDBUILD_NUM_LUT4=8 NGDBUILD_NUM_MUXCY=25 NGDBUILD_NUM_OBUF=11
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=26
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=29 NGDBUILD_NUM_FDE=7 NGDBUILD_NUM_FDR=3
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=1 NGDBUILD_NUM_LUT1=25
NGDBUILD_NUM_LUT2=2 NGDBUILD_NUM_LUT3=1 NGDBUILD_NUM_LUT4=8 NGDBUILD_NUM_MUXCY=25
NGDBUILD_NUM_OBUF=11 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=26
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s250e-4-cp132 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=500 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5