VGA Project Status
Project File: VGA_BACKGROUND.xise Parser Errors: No Errors
Module Name: VGA Implementation State: Programming File Generated
Target Device: xc3s250e-4cp132
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
20 Warnings (20 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 23 4,896 1%  
Number of 4 input LUTs 45 4,896 1%  
Number of occupied Slices 35 2,448 1%  
    Number of Slices containing only related logic 35 35 100%  
    Number of Slices containing unrelated logic 0 35 0%  
Total Number of 4 input LUTs 63 4,896 1%  
    Number used as logic 45      
    Number used as a route-thru 18      
Number of bonded IOBs 20 92 21%  
    IOB Flip Flops 8      
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 2.79      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Dec 29 22:41:03 2021000
Translation ReportCurrentWed Dec 29 22:41:08 2021000
Map ReportCurrentWed Dec 29 22:41:12 2021010 Warnings (10 new)2 Infos (2 new)
Place and Route ReportCurrentWed Dec 29 22:41:20 2021002 Infos (2 new)
Power Report     
Post-PAR Static Timing ReportCurrentWed Dec 29 22:41:23 2021006 Infos (6 new)
Bitgen ReportCurrentWed Dec 29 22:41:27 2021010 Warnings (10 new)0
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentWed Dec 29 22:41:27 2021
WebTalk Log FileCurrentWed Dec 29 22:41:32 2021

Date Generated: 12/29/2021 - 23:23:32