Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan3E
OS Platform: NT64 Target Device: xc3s250e
Project ID (random number) 55f081c80867439fa39bd3bfaa43cdb7.F0AA03B7BC944A1F949E44876228E300.5 Target Package: cp132
Registration ID __0_0_0 Target Speed: -4
Date Generated 2021-12-29T23:30:52 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i5-4288U CPU @ 2.60GHz CPU Speed 2594 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Comparators=6
  • 10-bit comparator less=1
  • 11-bit comparator greatequal=2
  • 11-bit comparator less=1
  • 11-bit comparator lessequal=2
 Counters=2
  • 10-bit up counter=2
 Registers=3
  • Flip-Flops=3
 		MiscellaneousStatistics
  • AGG_BONDED_IO=11
  • AGG_IO=11
  • AGG_SLICE=26
  • NUM_4_INPUT_LUT=49
  • NUM_BONDED_IBUF=1
  • NUM_BONDED_IOB=10
  • NUM_BUFGMUX=1
  • NUM_CYMUX=18
  • NUM_LUT_RT=18
  • NUM_SLICEL=26
  • NUM_SLICE_FF=23
  • NUM_XOR=20
 		NetStatistics
  • NumNets_Active=71
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=13
  • NumNodesOfType_Active_CNTRLPIN=23
  • NumNodesOfType_Active_DOUBLE=90
  • NumNodesOfType_Active_DUMMY=126
  • NumNodesOfType_Active_DUMMYESC=1
  • NumNodesOfType_Active_GLOBAL=11
  • NumNodesOfType_Active_HUNIHEX=4
  • NumNodesOfType_Active_INPUT=144
  • NumNodesOfType_Active_IOBOUTPUT=1
  • NumNodesOfType_Active_OMUX=62
  • NumNodesOfType_Active_OUTPUT=59
  • NumNodesOfType_Active_PREBXBY=28
  • NumNodesOfType_Active_VFULLHEX=7
  • NumNodesOfType_Active_VUNIHEX=8
  • NumNodesOfType_Gnd_INPUT=2
  • NumNodesOfType_Gnd_OMUX=2
  • NumNodesOfType_Gnd_OUTPUT=2
  • NumNodesOfType_Gnd_PREBXBY=5
 SiteStatistics
  • IBUF-DIFFMI=1
  • IOB-DIFFM=6
  • IOB-DIFFS=4
  • SLICEL-SLICEM=8
 		SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IBUF=1
  • IBUF_INBUF=1
  • IBUF_PAD=1
  • IOB=10
  • IOB_OUTBUF=10
  • IOB_PAD=10
  • SLICEL=26
  • SLICEL_C1VDD=2
  • SLICEL_CYMUXF=10
  • SLICEL_CYMUXG=8
  • SLICEL_F=25
  • SLICEL_FFX=12
  • SLICEL_FFY=11
  • SLICEL_G=24
  • SLICEL_GNDF=8
  • SLICEL_GNDG=8
  • SLICEL_XORF=10
  • SLICEL_XORG=10
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
 IBUF_PAD
  • IOATTRBOX=[LVCMOS25:1]
 IOB
  • O1=[O1_INV:0] [O1:10]
 IOB_OUTBUF
  • IN=[IN_INV:0] [IN:10]
 IOB_PAD
  • DRIVEATTRBOX=[2:10]
  • IOATTRBOX=[LVCMOS25:10]
  • PULL=[PULLUP:10]
  • SLEW=[SLOW:10]
 SLICEL
  • BX=[BX_INV:0] [BX:2]
  • BY=[BY:1] [BY_INV:0]
  • CE=[CE:5] [CE_INV:5]
  • CIN=[CIN_INV:0] [CIN:8]
  • CLK=[CLK:13] [CLK_INV:0]
  • SR=[SR:13] [SR_INV:0]
 SLICEL_CYMUXF
  • 0=[0:10] [0_INV:0]
  • 1=[1_INV:0] [1:10]
 SLICEL_CYMUXG
  • 0=[0:8] [0_INV:0]
 SLICEL_FFX
  • CE=[CE:5] [CE_INV:5]
  • CK=[CK:12] [CK_INV:0]
  • D=[D:12] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:12]
  • FFX_SR_ATTR=[SRLOW:12]
  • LATCH_OR_FF=[FF:12]
  • SR=[SR:12] [SR_INV:0]
  • SYNC_ATTR=[SYNC:12]
 SLICEL_FFY
  • CE=[CE:5] [CE_INV:5]
  • CK=[CK:11] [CK_INV:0]
  • D=[D:11] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:11]
  • FFY_SR_ATTR=[SRLOW:11]
  • LATCH_OR_FF=[FF:11]
  • SR=[SR:11] [SR_INV:0]
  • SYNC_ATTR=[SYNC:11]
 SLICEL_XORF
  • 1=[1_INV:0] [1:10]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
 BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
 BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
 IBUF
  • I=1
  • PAD=1
 IBUF_INBUF
  • IN=1
  • OUT=1
 IBUF_PAD
  • PAD=1
 IOB
  • O1=10
  • PAD=10
 IOB_OUTBUF
  • IN=10
  • OUT=10
 IOB_PAD
  • PAD=10
 SLICEL
  • BX=2
  • BY=1
  • CE=10
  • CIN=8
  • CLK=13
  • COUT=8
  • F1=25
  • F2=15
  • F3=14
  • F4=13
  • G1=24
  • G2=14
  • G3=12
  • G4=8
  • SR=13
  • X=13
  • XQ=12
  • Y=14
  • YQ=11
 SLICEL_C1VDD
  • 1=2
 SLICEL_CYMUXF
  • 0=10
  • 1=10
  • OUT=10
  • S0=10
 SLICEL_CYMUXG
  • 0=8
  • 1=8
  • OUT=8
  • S0=8
 SLICEL_F
  • A1=25
  • A2=15
  • A3=14
  • A4=13
  • D=25
 SLICEL_FFX
  • CE=10
  • CK=12
  • D=12
  • Q=12
  • SR=12
 SLICEL_FFY
  • CE=10
  • CK=11
  • D=11
  • Q=11
  • SR=11
 SLICEL_G
  • A1=24
  • A2=14
  • A3=12
  • A4=8
  • D=24
 SLICEL_GNDF
  • 0=8
 SLICEL_GNDG
  • 0=8
 SLICEL_XORF
  • 0=10
  • 1=10
  • O=10
 SLICEL_XORG
  • 0=10
  • 1=10
  • O=10
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s250e-cp132-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 31 31 0 0 0 0 0
arwz 1 1 0 0 0 0 0
bitgen 61 61 0 0 0 0 0
map 64 61 0 0 0 0 0
ngc2edif 1 1 0 0 0 0 0
ngdbuild 68 68 0 0 0 0 0
par 61 61 0 0 0 0 0
trce 61 61 0 0 0 0 0
xps 1 1 0 0 0 0 0
xst 97 97 0 0 0 0 0
 
Help Statistics
Search words with results
if ( 1 ) if statement ( 1 )
lut6 ( 1 )
Unsuccessful Search words
$readmemh ( 1 ) readmemh ( 1 )
Help files
/doc/usenglish/isehelp/ise_c_overview.htm ( 1 ) /doc/usenglish/isehelp/ite_c_overview.htm ( 2 )
/doc/usenglish/isehelp/ite_r_verilog_reserved_words.htm ( 1 ) /doc/usenglish/isehelp/rtv_db_lut_content.htm ( 1 )
/doc/usenglish/isehelp/rtv_p_rtl_lut_content.htm ( 1 )
 
Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000 PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2021-12-29T15:13:56 PROP_intWbtProjectID=F0AA03B7BC944A1F949E44876228E300
PROP_intWbtProjectIteration=5 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_xilxBitgStart_Clk=JTAG Clock
PROP_xilxBitgStart_IntDone=true PROP_AutoTop=true
PROP_DevFamily=Spartan3E PROP_DevDevice=xc3s250e
PROP_DevFamilyPMName=spartan3e PROP_DevPackage=cp132
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-4
PROP_PreferredLanguage=Verilog FILE_UCF=1
FILE_VERILOG=2
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDR=3 NGDBUILD_NUM_FDRE=20 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_INV=3 NGDBUILD_NUM_LUT1=18 NGDBUILD_NUM_LUT2=1 NGDBUILD_NUM_LUT2_L=2
NGDBUILD_NUM_LUT3=4 NGDBUILD_NUM_LUT3_L=1 NGDBUILD_NUM_LUT4=19 NGDBUILD_NUM_LUT4_D=1
NGDBUILD_NUM_LUT4_L=1 NGDBUILD_NUM_MUXCY=18 NGDBUILD_NUM_OBUF=10 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=20
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDR=3 NGDBUILD_NUM_FDRE=20 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=3 NGDBUILD_NUM_LUT1=18 NGDBUILD_NUM_LUT2=1
NGDBUILD_NUM_LUT2_L=2 NGDBUILD_NUM_LUT3=4 NGDBUILD_NUM_LUT3_L=1 NGDBUILD_NUM_LUT4=19
NGDBUILD_NUM_LUT4_D=1 NGDBUILD_NUM_LUT4_L=1 NGDBUILD_NUM_MUXCY=18 NGDBUILD_NUM_OBUF=10
NGDBUILD_NUM_PULLUP=10 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=20
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s250e-4-cp132 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=100000 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5