VGA Project Status
Project File: Polje3x3.xise Parser Errors: No Errors
Module Name: VGA Implementation State: Programming File Generated
Target Device: xc3s250e-4cp132
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 23 4,896 1%  
Number of 4 input LUTs 25 4,896 1%  
Number of occupied Slices 23 2,448 1%  
    Number of Slices containing only related logic 23 23 100%  
    Number of Slices containing unrelated logic 0 23 0%  
Total Number of 4 input LUTs 43 4,896 1%  
    Number used as logic 25      
    Number used as a route-thru 18      
Number of bonded IOBs 11 92 11%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 3.12      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Dec 29 23:14:01 202102 Warnings (2 new)0
Translation ReportCurrentWed Dec 29 23:14:06 2021000
Map ReportCurrentWed Dec 29 23:14:10 2021   
Place and Route ReportCurrentWed Dec 29 23:14:17 2021002 Infos (2 new)
Power Report     
Post-PAR Static Timing ReportCurrentWed Dec 29 23:14:20 2021006 Infos (6 new)
Bitgen ReportCurrentWed Dec 29 23:14:24 2021010 Warnings (10 new)0
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentWed Dec 29 23:14:24 2021
WebTalk Log FileCurrentWed Dec 29 23:14:28 2021

Date Generated: 12/29/2021 - 23:14:37