VerilogTest Project Status (07/13/2020 - 17:52:04) | |||
Project File: | VGA1.xise | Parser Errors: | No Errors |
Module Name: | VerilogTest | Implementation State: | Programming File Generated |
Target Device: | xc3s250e-4cp132 |
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No Errors |
Product Version: | ISE 14.7 |
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22 Warnings (20 new) |
Design Goal: | Balanced |
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All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
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All Constraints Met |
Environment: | System Settings |
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0 (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 23 | 4,896 | 1% | ||
Number of 4 input LUTs | 33 | 4,896 | 1% | ||
Number of occupied Slices | 28 | 2,448 | 1% | ||
Number of Slices containing only related logic | 28 | 28 | 100% | ||
Number of Slices containing unrelated logic | 0 | 28 | 0% | ||
Total Number of 4 input LUTs | 51 | 4,896 | 1% | ||
Number used as logic | 33 | ||||
Number used as a route-thru | 18 | ||||
Number of bonded IOBs | 11 | 92 | 11% | ||
Number of BUFGMUXs | 1 | 24 | 4% | ||
Average Fanout of Non-Clock Nets | 3.22 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Mon Jul 13 17:51:34 2020 | 0 | 2 Warnings (0 new) | 0 | |
Translation Report | Current | Mon Jul 13 17:51:40 2020 | 0 | 0 | 0 | |
Map Report | Current | Mon Jul 13 17:51:44 2020 | 0 | 10 Warnings (10 new) | 2 Infos (0 new) | |
Place and Route Report | Current | Mon Jul 13 17:51:52 2020 | 0 | 0 | 2 Infos (0 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | Mon Jul 13 17:51:56 2020 | 0 | 0 | 6 Infos (0 new) | |
Bitgen Report | Current | Mon Jul 13 17:52:00 2020 | 0 | 10 Warnings (10 new) | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Current | Mon Jul 13 17:52:01 2020 | |
WebTalk Log File | Current | Mon Jul 13 17:52:03 2020 |