LCD1 Project Status (07/06/2020 - 18:05:50)
Project File: LCD1.xise Parser Errors: No Errors
Module Name: LCD1 Implementation State: Programming File Generated
Target Device: xc3s250e-4cp132
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
20 Warnings (20 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Total Number Slice Registers 35 4,896 1%  
    Number used as Flip Flops 31      
    Number used as Latches 4      
Number of 4 input LUTs 22 4,896 1%  
Number of occupied Slices 24 2,448 1%  
    Number of Slices containing only related logic 24 24 100%  
    Number of Slices containing unrelated logic 0 24 0%  
Total Number of 4 input LUTs 39 4,896 1%  
    Number used as logic 22      
    Number used as a route-thru 17      
Number of bonded IOBs 15 92 16%  
Number of BUFGMUXs 2 24 8%  
Average Fanout of Non-Clock Nets 1.85      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Jul 6 18:11:10 2020018 Warnings (18 new)3 Infos (3 new)
Translation ReportCurrentMon Jul 6 18:11:16 2020000
Map ReportCurrentMon Jul 6 18:11:20 2020002 Infos (0 new)
Place and Route ReportCurrentMon Jul 6 18:11:28 202002 Warnings (2 new)2 Infos (1 new)
Power Report     
Post-PAR Static Timing ReportCurrentMon Jul 6 18:11:30 2020006 Infos (0 new)
Bitgen ReportCurrentMon Jul 6 18:11:34 2020000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentMon Jul 6 18:11:36 2020
WebTalk Log FileCurrentMon Jul 6 18:11:36 2020

Date Generated: 12/28/2020 - 11:06:59