LCD1 Project Status
Project File: LCD1.xise Parser Errors: No Errors
Module Name: LCD1 Implementation State: Programming File Generated
Target Device: xc3s250e-4cp132
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
3 Warnings (2 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 42 4,896 1%  
Number of 4 input LUTs 17 4,896 1%  
Number of occupied Slices 27 2,448 1%  
    Number of Slices containing only related logic 27 27 100%  
    Number of Slices containing unrelated logic 0 27 0%  
Total Number of 4 input LUTs 48 4,896 1%  
    Number used as logic 17      
    Number used as a route-thru 31      
Number of bonded IOBs 12 92 13%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 2.30      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Jun 22 19:22:30 202001 Warning (1 new)1 Info (0 new)
Translation ReportCurrentMon Jun 22 19:22:36 2020000
Map ReportCurrentMon Jun 22 19:22:40 2020002 Infos (0 new)
Place and Route ReportCurrentMon Jun 22 19:22:48 202002 Warnings (1 new)2 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentMon Jun 22 19:22:50 2020006 Infos (0 new)
Bitgen ReportCurrentMon Jun 22 19:22:56 2020000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentMon Jun 22 19:22:56 2020
WebTalk Log FileCurrentMon Jun 22 19:22:58 2020

Date Generated: 12/28/2020 - 10:36:56