Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan3E
OS Platform: NT64 Target Device: xc3s250e
Project ID (random number) 4dced80102c340b492e86a458f945666.FD7A63142A9F4388B401E1A6CEDE89FB.5 Target Package: cp132
Registration ID 211696053_0_0_613 Target Speed: -4
Date Generated 2020-06-22T18:44:05 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i3-4170 CPU @ 3.70GHz CPU Speed 3691 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Counters=2
  • 26-bit up counter=1
  • 4-bit up counter=1
ROMs=1
  • 16x7-bit ROM=1
MiscellaneousStatistics
  • AGG_BONDED_IO=12
  • AGG_IO=12
  • AGG_SLICE=19
  • NUM_4_INPUT_LUT=36
  • NUM_BONDED_IBUF=1
  • NUM_BONDED_IOB=11
  • NUM_BUFGMUX=1
  • NUM_CYMUX=25
  • NUM_LUT_RT=25
  • NUM_SLICEL=19
  • NUM_SLICE_FF=30
  • NUM_XOR=26
NetStatistics
  • NumNets_Active=63
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=16
  • NumNodesOfType_Active_CNTRLPIN=1
  • NumNodesOfType_Active_DOUBLE=26
  • NumNodesOfType_Active_DUMMY=64
  • NumNodesOfType_Active_DUMMYESC=1
  • NumNodesOfType_Active_GLOBAL=8
  • NumNodesOfType_Active_HFULLHEX=1
  • NumNodesOfType_Active_HLONG=1
  • NumNodesOfType_Active_INPUT=83
  • NumNodesOfType_Active_IOBOUTPUT=1
  • NumNodesOfType_Active_OMUX=38
  • NumNodesOfType_Active_OUTPUT=50
  • NumNodesOfType_Active_PREBXBY=7
  • NumNodesOfType_Active_VFULLHEX=2
  • NumNodesOfType_Active_VLONG=1
  • NumNodesOfType_Active_VUNIHEX=4
  • NumNodesOfType_Gnd_DOUBLE=1
  • NumNodesOfType_Gnd_INPUT=2
  • NumNodesOfType_Gnd_OMUX=1
  • NumNodesOfType_Gnd_OUTPUT=2
  • NumNodesOfType_Gnd_PREBXBY=1
SiteStatistics
  • IBUF-DIFFMI=1
  • IOB-DIFFM=5
  • IOB-DIFFS=6
  • SLICEL-SLICEM=3
SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IBUF=1
  • IBUF_INBUF=1
  • IBUF_PAD=1
  • IOB=11
  • IOB_OUTBUF=11
  • IOB_PAD=11
  • SLICEL=19
  • SLICEL_C1VDD=1
  • SLICEL_CYMUXF=13
  • SLICEL_CYMUXG=12
  • SLICEL_F=18
  • SLICEL_FFX=14
  • SLICEL_FFY=16
  • SLICEL_G=18
  • SLICEL_GNDF=12
  • SLICEL_GNDG=12
  • SLICEL_XORF=13
  • SLICEL_XORG=13
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:1]
IOB
  • O1=[O1_INV:0] [O1:11]
IOB_OFF1
  • CE=[CE:0] [CE_INV:7]
  • CK=[CK:7] [CK_INV:0]
  • D=[D:7] [D_INV:0]
  • LATCH_OR_FF=[LATCH:7]
  • OFF1_INIT_ATTR=[INIT0:7]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:11]
IOB_PAD
  • DRIVEATTRBOX=[12:11]
  • IOATTRBOX=[LVCMOS25:11]
  • SLEW=[SLOW:11]
SLICEL
  • BX=[BX_INV:0] [BX:1]
  • BY=[BY:1] [BY_INV:0]
  • CIN=[CIN_INV:0] [CIN:12]
  • CLK=[CLK:16] [CLK_INV:0]
  • SR=[SR:1] [SR_INV:0]
SLICEL_CYMUXF
  • 0=[0:13] [0_INV:0]
  • 1=[1_INV:0] [1:13]
SLICEL_CYMUXG
  • 0=[0:12] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:1] [S0_INV:0]
SLICEL_FFX
  • CK=[CK:14] [CK_INV:0]
  • D=[D:14] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:14]
  • FFX_SR_ATTR=[SRLOW:14]
  • LATCH_OR_FF=[FF:14]
  • SYNC_ATTR=[ASYNC:14]
SLICEL_FFY
  • CK=[CK:16] [CK_INV:0]
  • D=[D:16] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:16]
  • FFY_SR_ATTR=[SRLOW:16]
  • LATCH_OR_FF=[FF:16]
  • SR=[SR:1] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:15] [SYNC:1]
SLICEL_XORF
  • 1=[1_INV:0] [1:13]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
IBUF
  • I=1
  • PAD=1
IBUF_INBUF
  • IN=1
  • OUT=1
IBUF_PAD
  • PAD=1
IOB
  • O1=11
  • PAD=11
IOB_OFF1
  • CE=7
  • CK=7
  • D=7
  • Q=7
IOB_OUTBUF
  • IN=11
  • OUT=11
IOB_PAD
  • PAD=11
SLICEL
  • BX=1
  • BY=1
  • CIN=12
  • CLK=16
  • COUT=12
  • F1=18
  • F2=5
  • F3=5
  • F4=5
  • G1=18
  • G2=5
  • G3=4
  • G4=3
  • SR=1
  • X=4
  • XQ=14
  • Y=3
  • YQ=16
SLICEL_C1VDD
  • 1=1
SLICEL_CYMUXF
  • 0=13
  • 1=13
  • OUT=13
  • S0=13
SLICEL_CYMUXG
  • 0=12
  • 1=12
  • OUT=12
  • S0=12
SLICEL_F
  • A1=18
  • A2=5
  • A3=5
  • A4=5
  • D=18
SLICEL_F5MUX
  • F=1
  • G=1
  • OUT=1
  • S0=1
SLICEL_FFX
  • CK=14
  • D=14
  • Q=14
SLICEL_FFY
  • CK=16
  • D=16
  • Q=16
  • SR=1
SLICEL_G
  • A1=18
  • A2=5
  • A3=4
  • A4=3
  • D=18
SLICEL_GNDF
  • 0=12
SLICEL_GNDG
  • 0=12
SLICEL_XORF
  • 0=13
  • 1=13
  • O=13
SLICEL_XORG
  • 0=13
  • 1=13
  • O=13
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s250e-cp132-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s250e-cp132-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s250e-cp132-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s250e-cp132-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s250e-cp132-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
bitgen 20 20 0 0 0 0 0
map 18 18 0 0 0 0 0
ngdbuild 20 20 0 0 0 0 0
par 18 18 0 0 0 0 0
trce 18 18 0 0 0 0 0
xst 17 17 0 0 0 0 0
 
Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000 PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2020-06-08T19:03:38 PROP_intWbtProjectID=FD7A63142A9F4388B401E1A6CEDE89FB
PROP_intWbtProjectIteration=5 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_lockPinsUcfFile=changed
PROP_xilxBitgStart_Clk=JTAG Clock PROP_xilxBitgStart_IntDone=true
PROP_AutoTop=true PROP_DevFamily=Spartan3E
PROP_DevDevice=xc3s250e PROP_DevFamilyPMName=spartan3e
PROP_DevPackage=cp132 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-4 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=29 NGDBUILD_NUM_FDR=1 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_INV=1 NGDBUILD_NUM_LUT1=25 NGDBUILD_NUM_LUT2=1 NGDBUILD_NUM_LUT3=1
NGDBUILD_NUM_LUT4=8 NGDBUILD_NUM_MUXCY=25 NGDBUILD_NUM_OBUF=11 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=26
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=29 NGDBUILD_NUM_FDR=1 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=1 NGDBUILD_NUM_LUT1=25 NGDBUILD_NUM_LUT2=1
NGDBUILD_NUM_LUT3=1 NGDBUILD_NUM_LUT4=8 NGDBUILD_NUM_MUXCY=25 NGDBUILD_NUM_OBUF=11
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=26
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s250e-4-cp132 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=100000 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5