LCD1 Project Status
Project File: LCD1.xise Parser Errors: No Errors
Module Name: LCD1 Implementation State: Programming File Generated
Target Device: xc3s250e-4cp132
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of 4 input LUTs 7 4,896 1%  
Number of occupied Slices 4 2,448 1%  
    Number of Slices containing only related logic 4 4 100%  
    Number of Slices containing unrelated logic 0 4 0%  
Total Number of 4 input LUTs 7 4,896 1%  
Number of bonded IOBs 19 92 20%  
Average Fanout of Non-Clock Nets 2.60      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Jun 22 17:25:12 2020000
Translation ReportCurrentMon Jun 22 17:25:20 2020000
Map ReportCurrentMon Jun 22 17:25:26 2020002 Infos (0 new)
Place and Route ReportCurrentMon Jun 22 17:25:34 2020001 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentMon Jun 22 17:25:36 2020006 Infos (0 new)
Bitgen ReportCurrentMon Jun 22 17:25:42 2020000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentMon Jun 22 17:25:42 2020
WebTalk Log FileCurrentMon Jun 22 17:25:44 2020

Date Generated: 12/28/2020 - 09:50:58