VerilogTest Project Status
Project File: VGA1.xise Parser Errors: No Errors
Module Name: VerilogTest Implementation State: Programming File Generated
Target Device: xc3s250e-4cp132
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
20 Warnings (20 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 23 4,896 1%  
Number of 4 input LUTs 30 4,896 1%  
Number of occupied Slices 26 2,448 1%  
    Number of Slices containing only related logic 26 26 100%  
    Number of Slices containing unrelated logic 0 26 0%  
Total Number of 4 input LUTs 48 4,896 1%  
    Number used as logic 30      
    Number used as a route-thru 18      
Number of bonded IOBs 19 92 20%  
    IOB Flip Flops 8      
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 2.72      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Jul 6 19:27:20 2020000
Translation ReportCurrentMon Jul 6 19:28:19 2020000
Map ReportCurrentMon Jul 6 19:28:24 2020010 Warnings (10 new)2 Infos (2 new)
Place and Route ReportCurrentMon Jul 6 19:28:32 2020002 Infos (2 new)
Power Report     
Post-PAR Static Timing ReportCurrentMon Jul 6 19:28:35 2020006 Infos (6 new)
Bitgen ReportCurrentMon Jul 6 19:28:39 2020010 Warnings (10 new)0
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentMon Jul 6 19:28:40 2020
WebTalk Log FileCurrentMon Jul 6 19:28:42 2020

Date Generated: 07/13/2020 - 17:12:04