VerilogTest Project Status (07/13/2020 - 18:29:03)
Project File: VGA1.xise Parser Errors: No Errors
Module Name: VerilogTest Implementation State: Programming File Generated
Target Device: xc3s250e-4cp132
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
21 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 23 4,896 1%  
Number of 4 input LUTs 31 4,896 1%  
Number of occupied Slices 26 2,448 1%  
    Number of Slices containing only related logic 26 26 100%  
    Number of Slices containing unrelated logic 0 26 0%  
Total Number of 4 input LUTs 49 4,896 1%  
    Number used as logic 31      
    Number used as a route-thru 18      
Number of bonded IOBs 11 92 11%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 3.21      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Jul 13 18:28:35 202001 Warning (0 new)0
Translation ReportCurrentMon Jul 13 18:28:41 2020000
Map ReportCurrentMon Jul 13 18:28:45 2020010 Warnings (0 new)2 Infos (0 new)
Place and Route ReportCurrentMon Jul 13 18:28:53 2020002 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentMon Jul 13 18:28:56 2020006 Infos (0 new)
Bitgen ReportCurrentMon Jul 13 18:29:01 2020010 Warnings (0 new)0
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentMon Jul 13 18:29:01 2020
WebTalk Log FileCurrentMon Jul 13 18:29:03 2020

Date Generated: 07/13/2020 - 18:29:03