LCD1 Project Status (07/06/2020 - 18:05:50)
Project File: LCD1.xise Parser Errors: No Errors
Module Name: LCD1 Implementation State: Programming File Generated
Target Device: xc3s250e-4cp132
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
5 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 31 4,896 1%  
Number of 4 input LUTs 36 4,896 1%  
Number of occupied Slices 32 2,448 1%  
    Number of Slices containing only related logic 32 32 100%  
    Number of Slices containing unrelated logic 0 32 0%  
Total Number of 4 input LUTs 53 4,896 1%  
    Number used as logic 36      
    Number used as a route-thru 17      
Number of bonded IOBs 20 92 21%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 2.36      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Jul 6 18:26:18 202004 Warnings (0 new)2 Infos (1 new)
Translation ReportCurrentMon Jul 6 18:26:22 2020000
Map ReportCurrentMon Jul 6 18:26:26 2020002 Infos (0 new)
Place and Route ReportCurrentMon Jul 6 18:26:34 202001 Warning (0 new)2 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentMon Jul 6 18:26:36 2020006 Infos (0 new)
Bitgen ReportCurrentMon Jul 6 18:26:42 2020000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentMon Jul 6 18:26:42 2020
WebTalk Log FileCurrentMon Jul 6 18:26:42 2020

Date Generated: 12/28/2020 - 11:07:34