drugiOV Project Status
Project File: drugiOV.xise Parser Errors: No Errors
Module Name: drugiOV Implementation State: Programming File Generated
Target Device: xc3s250e-4cp132
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of 4 input LUTs 1 4,896 1%  
Number of occupied Slices 1 2,448 1%  
    Number of Slices containing only related logic 1 1 100%  
    Number of Slices containing unrelated logic 0 1 0%  
Total Number of 4 input LUTs 1 4,896 1%  
Number of bonded IOBs 3 92 3%  
Average Fanout of Non-Clock Nets 1.00      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Jun 1 18:27:44 2020000
Translation ReportCurrentMon Jun 1 18:27:48 2020000
Map ReportCurrentMon Jun 1 18:27:52 2020002 Infos (2 new)
Place and Route ReportCurrentMon Jun 1 18:27:58 2020001 Info (1 new)
Power Report     
Post-PAR Static Timing ReportCurrentMon Jun 1 18:28:02 2020006 Infos (6 new)
Bitgen ReportCurrentMon Jun 1 18:28:06 2020000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentMon Jun 1 18:28:06 2020
WebTalk Log FileCurrentMon Jun 1 18:28:08 2020

Date Generated: 12/28/2020 - 09:10:44