VerilogTest Project Status (07/12/2020 - 23:32:07) | |||
Project File: | VGA1.xise | Parser Errors: | No Errors |
Module Name: | VerilogTest | Implementation State: | Synthesized (Failed) |
Target Device: | xc3s250e-4cp132 |
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X 5 Errors (5 new) |
Product Version: | ISE 14.7 |
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No Warnings |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | ned 12. jul 23:32:06 2020 | X 5 Errors (5 new) | 0 | 0 | |
Translation Report | Out of Date | pon 6. jul 19:28:20 2020 | 0 | 0 | 0 | |
Map Report | Out of Date | pon 6. jul 19:28:26 2020 | 0 | 10 Warnings (10 new) | 2 Infos (2 new) | |
Place and Route Report | Out of Date | pon 6. jul 19:28:34 2020 | 0 | 0 | 2 Infos (2 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Out of Date | pon 6. jul 19:28:36 2020 | 0 | 0 | 6 Infos (6 new) | |
Bitgen Report | Out of Date | pon 6. jul 19:28:40 2020 | 0 | 10 Warnings (10 new) | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Out of Date | pon 6. jul 19:28:42 2020 | |
WebTalk Log File | Out of Date | pon 6. jul 19:28:44 2020 |