VerilogTest Project Status (07/12/2020 - 23:32:07)
Project File: VGA1.xise Parser Errors: No Errors
Module Name: VerilogTest Implementation State: Synthesized (Failed)
Target Device: xc3s250e-4cp132
  • Errors:
X 5 Errors (5 new)
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentned 12. jul 23:32:06 2020X 5 Errors (5 new)00
Translation ReportOut of Datepon 6. jul 19:28:20 2020000
Map ReportOut of Datepon 6. jul 19:28:26 2020010 Warnings (10 new)2 Infos (2 new)
Place and Route ReportOut of Datepon 6. jul 19:28:34 2020002 Infos (2 new)
Power Report     
Post-PAR Static Timing ReportOut of Datepon 6. jul 19:28:36 2020006 Infos (6 new)
Bitgen ReportOut of Datepon 6. jul 19:28:40 2020010 Warnings (10 new)0
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of Datepon 6. jul 19:28:42 2020
WebTalk Log FileOut of Datepon 6. jul 19:28:44 2020

Date Generated: 07/12/2020 - 23:32:08