`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:17:50 05/04/2022 
// Design Name: 
// Module Name:    vga_rom 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module vga_rom(
	input wire clk,
	input wire [4:0] addr,
	output reg [7:0] data
    );

(* rom_style = "block" *)

reg [4:0] addr_reg;

always @(posedge clk)
	addr_reg <= addr;

always @(*)
case(addr_reg)
5'd0: data = 8'h41;
5'd1: data = 8'h3a;
5'd2: data = 8'h20;
5'd3: data = 8'h20;
5'd4: data = 8'h42;
5'd5: data = 8'h3a;
5'd6: data = 8'h20;
5'd7: data = 8'h20;
5'd8: data = 8'h4f;
5'd9: data = 8'h50;
5'd10: data = 8'h45;
5'd11: data = 8'h52;
5'd12: data = 8'h41;
5'd13: data = 8'h43;
5'd14: data = 8'h49;
5'd15: data = 8'h4a;
5'd16: data = 8'h41;
5'd17: data = 8'h3a;
5'd18: data = 8'h20;
5'd19: data = 8'h20;
5'd20: data = 8'h52;
5'd21: data = 8'h45;
5'd22: data = 8'h5a;
5'd23: data = 8'h55;
5'd24: data = 8'h4c;
5'd25: data = 8'h54;
5'd26: data = 8'h41;
5'd27: data = 8'h54;
5'd28: data = 8'h3a;
5'd29: data = 8'h20;
5'd30: data = 8'h20;
5'd31: data = 8'h2e;
endcase
endmodule