`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    00:21:03 04/24/2022 
// Design Name: 
// Module Name:    ALU74181 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module ALU74181(
	input wire clk,
	input wire [3:0] S,
	input wire Cn, 
	input wire M,
	input wire [3:0] A, 
	input wire [3:0] B,
	output reg [3:0] F
);

    reg [3:0] P, G;

    always @(posedge clk) 
	 begin

    P[0] <= ~(A[0] | (S[0] & B[0]) | (S[1] & ~B[0]));
    P[1] <= ~(A[1] | (S[0] & B[1]) | (S[1] & ~B[1]));
    P[2] <= ~(A[2] | (S[0] & B[2]) | (S[1] & ~B[2]));
    P[3] <= ~(A[3] | (S[0] & B[3]) | (S[1] & ~B[3]));

    G[0] <= ~((A[0] & ~B[0] & S[2]) | (A[0] & B[0] & S[3]));
    G[1] <= ~((A[1] & ~B[1] & S[2]) | (A[1] & B[1] & S[3]));
    G[2] <= ~((A[2] & ~B[2] & S[2]) | (A[2] & B[2] & S[3]));
    G[3] <= ~((A[3] & ~B[3] & S[2]) | (A[3] & B[3] & S[3]));

    F[0] <= (P[0] ^ G[0]) ^ ~(Cn & ~M);
    F[1] <= (P[1] ^ G[1]) ^ ~((Cn & ~M & G[0]) | (~M & P[0]));
    F[2] <= (P[2] ^ G[2]) ^ ~((Cn & ~M & G[0] & G[1]) | (~M & P[1]) | (~M & P[0] & G[1]));
    F[3] <= (P[3] ^ G[3]) ^ ~((Cn & ~M & G[0] & G[1] & G[2]) | (~M & P[2]) | (~M & P[1] & G[2]) | (~M & P[0] & G[1] & G[2]));
    end
endmodule