`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    08:33:42 04/20/2023 
// Design Name: 
// Module Name:    Zad26 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Zad26(
	output reg [6:0] F,
	output reg [3:0] an,
	input wire clk,
	input wire [3:0] prekidaci
    );

reg [15:0] brojac = 16'b0;
reg [2:0] brojac_anode = 3'b0;

always @(posedge clk)
brojac <= brojac + 1'b1;

reg [15:0] rezultat = 16'b0;

always @(posedge clk)
begin
if(prekidaci == 4'b0)
rezultat <= 16'd100 + 16'd64;

if(prekidaci == 4'b0001)
rezultat <= 16'd1 + 16'd1;

if(prekidaci == 4'b0010)
rezultat <= 16'd100 - 16'd64;

if(prekidaci == 4'b0011)
rezultat <= 16'd32;
end

always @(posedge brojac[15])
begin
brojac_anode <= brojac_anode + 1'b1;
if(brojac_anode == 0) an <= ~(4'b0000);
if(brojac_anode == 1) an <= ~(4'b0001);
if(brojac_anode == 2) an <= ~(4'b0000);
if(brojac_anode == 3) an <= ~(4'b0010);
if(brojac_anode == 4) an <= ~(4'b0000);
if(brojac_anode == 5) an <= ~(4'b0100);
if(brojac_anode == 6) an <= ~(4'b0000);
if(brojac_anode == 7) an <= ~(4'b1000);

if(brojac_anode == 1)
case(rezultat[3:0])
4'b0000:F <= ~7'b011_1111;
4'b0001:F <= ~7'b000_0110;
4'b0010:F <= ~7'b101_1011;
4'b0011:F <= ~7'b100_1111;
4'b0100:F <= ~7'b110_0110;
4'b0101:F <= ~7'b110_1101;
4'b0110:F <= ~7'b111_1101;
4'b0111:F <= ~7'b000_0111;
4'b1000:F <= ~7'b111_1111;
4'b1001:F <= ~7'b110_1111;
4'b1010:F <= ~7'b111_0111;
4'b1011:F <= ~7'b111_1100;
4'b1100:F <= ~7'b011_1001;
4'b1101:F <= ~7'b101_1110;
4'b1110:F <= ~7'b111_1001;
4'b1111:F <= ~7'b111_0001;
endcase

if(brojac_anode == 3)
case(rezultat[7:4])
4'b0000:F <= ~7'b011_1111;
4'b0001:F <= ~7'b000_0110;
4'b0010:F <= ~7'b101_1011;
4'b0011:F <= ~7'b100_1111;
4'b0100:F <= ~7'b110_0110;
4'b0101:F <= ~7'b110_1101;
4'b0110:F <= ~7'b111_1101;
4'b0111:F <= ~7'b000_0111;
4'b1000:F <= ~7'b111_1111;
4'b1001:F <= ~7'b110_1111;
4'b1010:F <= ~7'b111_0111;
4'b1011:F <= ~7'b111_1100;
4'b1100:F <= ~7'b011_1001;
4'b1101:F <= ~7'b101_1110;
4'b1110:F <= ~7'b111_1001;
4'b1111:F <= ~7'b111_0001;
endcase

if(brojac_anode == 5)
case(rezultat[11:8])
4'b0000:F <= ~7'b011_1111;
4'b0001:F <= ~7'b000_0110;
4'b0010:F <= ~7'b101_1011;
4'b0011:F <= ~7'b100_1111;
4'b0100:F <= ~7'b110_0110;
4'b0101:F <= ~7'b110_1101;
4'b0110:F <= ~7'b111_1101;
4'b0111:F <= ~7'b000_0111;
4'b1000:F <= ~7'b111_1111;
4'b1001:F <= ~7'b110_1111;
4'b1010:F <= ~7'b111_0111;
4'b1011:F <= ~7'b111_1100;
4'b1100:F <= ~7'b011_1001;
4'b1101:F <= ~7'b101_1110;
4'b1110:F <= ~7'b111_1001;
4'b1111:F <= ~7'b111_0001;
endcase

if(brojac_anode == 7)
case(rezultat[15:12])
4'b0000:F <= ~7'b011_1111;
4'b0001:F <= ~7'b000_0110;
4'b0010:F <= ~7'b101_1011;
4'b0011:F <= ~7'b100_1111;
4'b0100:F <= ~7'b110_0110;
4'b0101:F <= ~7'b110_1101;
4'b0110:F <= ~7'b111_1101;
4'b0111:F <= ~7'b000_0111;
4'b1000:F <= ~7'b111_1111;
4'b1001:F <= ~7'b110_1111;
4'b1010:F <= ~7'b111_0111;
4'b1011:F <= ~7'b111_1100;
4'b1100:F <= ~7'b011_1001;
4'b1101:F <= ~7'b101_1110;
4'b1110:F <= ~7'b111_1001;
4'b1111:F <= ~7'b111_0001;
endcase
end

endmodule