`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    09:18:07 03/30/2023 
// Design Name: 
// Module Name:    Zad22 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Zad22(
    output reg [6:0] F,
    output wire DP,
    output wire [3:0] anode,
    input wire clk
    );
	 
reg [23:0] brojac = 24'b0;
reg [3:0] frejm = 4'b0;
reg [3:0] an = 4'b0001;
reg [2:0] brojac_anode = 3'b0;


always @(posedge clk)
brojac <= brojac + 1'b1;

always @(posedge brojac[23])
frejm <= frejm + 1'b1;

always @(posedge brojac[15])
begin
brojac_anode <= brojac_anode + 1'b1;
if(brojac_anode == 0) an <= 4'b0000;
if(brojac_anode == 1) an <= 4'b0001;
if(brojac_anode == 2) an <= 4'b0000;
if(brojac_anode == 3) an <= 4'b0010;
if(brojac_anode == 4) an <= 4'b0000;
if(brojac_anode == 5) an <= 4'b0100;
if(brojac_anode == 6) an <= 4'b0000;
if(brojac_anode == 7) an <= 4'b1000;

if(brojac_anode == 1)
case(frejm)
4'b0000:F <= ~7'b100_0000;
4'b0001:F <= ~7'b000_0000;
4'b0010:F <= ~7'b000_0000;
4'b0011:F <= ~7'b000_0000;
4'b0100:F <= ~7'b000_0000;
4'b0101:F <= ~7'b000_0000;
4'b0110:F <= ~7'b000_0000;
4'b0111:F <= ~7'b000_0000;
4'b1000:F <= ~7'b000_0000;
4'b1001:F <= ~7'b000_0000;
4'b1010:F <= ~7'b000_0000;
4'b1011:F <= ~7'b000_0000;
4'b1100:F <= ~7'b000_0000;
4'b1101:F <= ~7'b000_0000;
4'b1110:F <= ~7'b000_1000;
4'b1111:F <= ~7'b000_0100;
endcase

if(brojac_anode == 3)
case(frejm)
4'b0000:F <= ~7'b000_0000;
4'b0001:F <= ~7'b100_0000;
4'b0010:F <= ~7'b000_0000;
4'b0011:F <= ~7'b000_0000;
4'b0100:F <= ~7'b000_0000;
4'b0101:F <= ~7'b000_0000;
4'b0110:F <= ~7'b000_0000;
4'b0111:F <= ~7'b000_0000;
4'b1000:F <= ~7'b000_0000;
4'b1001:F <= ~7'b000_0000;
4'b1010:F <= ~7'b000_0000;
4'b1011:F <= ~7'b000_0001;
4'b1100:F <= ~7'b000_0010;
4'b1101:F <= ~7'b000_0100;
4'b1110:F <= ~7'b000_0000;
4'b1111:F <= ~7'b000_0000;
endcase

if(brojac_anode == 5)
case(frejm)
4'b0000:F <= ~7'b000_0000;
4'b0001:F <= ~7'b000_0000;
4'b0010:F <= ~7'b100_0000;
4'b0011:F <= ~7'b000_0000;
4'b0100:F <= ~7'b000_0000;
4'b0101:F <= ~7'b000_0000;
4'b0110:F <= ~7'b000_0000;
4'b0111:F <= ~7'b000_0000;
4'b1000:F <= ~7'b000_1000;
4'b1001:F <= ~7'b000_0100;
4'b1010:F <= ~7'b000_0010;
4'b1011:F <= ~7'b000_0000;
4'b1100:F <= ~7'b000_0000;
4'b1101:F <= ~7'b000_0000;
4'b1110:F <= ~7'b000_0000;
4'b1111:F <= ~7'b000_0000;
endcase

if(brojac_anode == 7)
case(frejm)
4'b0000:F <= ~7'b000_0000;
4'b0001:F <= ~7'b000_0000;
4'b0010:F <= ~7'b000_0000;
4'b0011:F <= ~7'b100_0000;
4'b0100:F <= ~7'b010_0000;
4'b0101:F <= ~7'b000_0001;
4'b0110:F <= ~7'b000_0010;
4'b0111:F <= ~7'b000_0100;
4'b1000:F <= ~7'b000_0000;
4'b1001:F <= ~7'b000_0000;
4'b1010:F <= ~7'b000_0000;
4'b1011:F <= ~7'b000_0000;
4'b1100:F <= ~7'b000_0000;
4'b1101:F <= ~7'b000_0000;
4'b1110:F <= ~7'b000_0000;
4'b1111:F <= ~7'b000_0000;
endcase

end

assign anode = ~an;
assign DP = 1'b1;

endmodule