`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    09:58:02 04/13/2022 
// Design Name: 
// Module Name:    vga_controller_640x480_60Hz 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module vga_controller_640x480_60Hz(
	input wire clk50MHz,
	output reg hsync,
	output reg vsync,
	output reg video_on,
	output reg [9:0] x,
	output reg [9:0] y,
	output wire pix_clk
    );

reg pixel_clk;

always @(posedge clk50MHz)
	pixel_clk <= pixel_clk + 1'b1;

always @(posedge pixel_clk)
begin
	if(x < 799)
		x <= x + 1'b1;
	else
		begin
			x <= 0;
			y <= y == 524 ? 10'b0 : y + 1'b1;
		end
end

always @*
begin
	hsync <= ~(x > 654 && x < 751);
	vsync <= ~(y > 488 && y < 491);
	video_on <= x < 640 && y < 480;
end

assign pix_clk = ~pixel_clk;

endmodule