module sevensegment(input wire clock, input wire [4:0] data, input wire [2:0] digit, input wire setdp, output wire AN0, AN1, AN2, AN3, CA, CB, CC , CD, CE, CF, CG, CDP);

reg [7:0] cathodedata = 8'b00000011;
reg [3:0] anodedata = 4'b1111;

always @(negedge clock)
begin
case(data)
	0: cathodedata = 8'b00000011;
	1: cathodedata = 8'b10011111;
	2: cathodedata = 8'b00100101;
	3: cathodedata = 8'b00001101;
	4: cathodedata = 8'b10011001;
	5: cathodedata = 8'b01001001;
	6: cathodedata = 8'b01000001;
	7: cathodedata = 8'b00011111;
	8: cathodedata = 8'b00000001;
	9: cathodedata = 8'b00001001;
	10: cathodedata = 8'b00010001;
	11: cathodedata = 8'b11000001;
	12: cathodedata = 8'b01100011;
	13: cathodedata = 8'b10000101;
	14: cathodedata = 8'b01100001;
	15: cathodedata = 8'b01110001;
	16: cathodedata = 8'b11111101;
	17: cathodedata = 8'b01111111;
	18: cathodedata = 8'b10111111;
	19: cathodedata = 8'b11011111;
	20: cathodedata = 8'b11101111;
	21: cathodedata = 8'b11110111;
	22: cathodedata = 8'b11111011;
	23: cathodedata = 8'b11011001;
	24: cathodedata = 8'b10110101;
	25: cathodedata = 8'b11000101;
	26: cathodedata = 8'b00111001;
	27: cathodedata = 8'b11010101;
	28: cathodedata = 8'b10111001;
	29: cathodedata = 8'b11000111;
	30: cathodedata = 8'b00111011;
	31: cathodedata = 8'b11111111;
endcase

if(setdp == 1)
	cathodedata = cathodedata & 8'hFE;

case (digit)
	0: anodedata = 4'b1111;
	1: anodedata = 4'b1110;
	2: anodedata = 4'b1101;
	3: anodedata = 4'b1011;
	4: anodedata = 4'b0111;
default: anodedata = 4'b1111;
endcase

end

assign CA = cathodedata[7];
assign CB = cathodedata[6];
assign CC = cathodedata[5];
assign CD = cathodedata[4];
assign CE = cathodedata[3];
assign CF = cathodedata[2];
assign CG = cathodedata[1];
assign CDP = cathodedata[0];

assign AN3 = anodedata[3];
assign AN2 = anodedata[2];
assign AN1 = anodedata[1];
assign AN0 = anodedata[0];
endmodule