module checkkbd(input wire clk, output reg [4:0] data, output reg [2:0] digit, output reg setdp, input wire dav, input wire [7:0] kbddata, input wire parity);

reg [1:0] digitmux = 0;
reg [3:0] msdigit;
reg [3:0] lsdigit;
reg chkparity, dataav;

integer i;

always @(posedge dav)
begin
	dataav = 0;
	msdigit[3:0] <= kbddata[7:4];
	lsdigit[3:0] <= kbddata[3:0];
	chkparity = kbddata[0] ^ kbddata[1];
	for(i=2;i<=7;i=i+1)
		chkparity = kbddata[i] ^ chkparity;
	chkparity = parity ^ chkparity;
	dataav = 1;
end

always @(posedge clk)
begin
	if(dataav)
	begin
		digitmux = digitmux + 1;
		setdp = digitmux[1];
		data[4] <= 0;

		case(digitmux)
		0: begin
			data[3:0] <= lsdigit;
			digit <= 1;
			end
		1: begin
			data[3:0] <= msdigit;
			digit <= 2;
			end
		2: begin
			data[0] <= chkparity;
			data[3:1] <= 3'b000;
			digit <= 3;
			end
		3: begin
			data[0] <= parity;
			data[3:1] <= 3'b000;
			digit <= 4;
			end

		endcase
	end

end

endmodule